OK...little explanation here

[CaterpillarAssassin]

I remember back in the day AMD's chips supposedly ran at 200mhz and 266mhz bus. But only needed pc100 and pc133 ram respectively. Why was that the case again?

Now once that is explained does that same principle that applies to say the P4's with "333mhz bus" and so on?

[Busby]

DDR. Double Data Rate. 100x2 = 200, 133x2 = 266

AMD Athlons would take advantage of DDR themselves before DDR RAM came out. I believe that DDR makes seperate channels for like writing and reading, kind of like what Full Duplex does for networking, allowing a seperate channel for uploading and downloading, effectively doubling the throughput.

[PreDatoR]

the athlons have always had a dual pumped FSB... 200 and 266 PC100 and 133 didn't give the chip enough memory bandwidth so everything went to DDR that would give it its bandwidth. P4's have a quad pumped bus of 400 and 533 so if the FSB is set at 100 the chip is actually at 400 fsb. Ram has been a prob with the p4's. Rambus will give the chip enough memory bandwidth while using DDR is a slight bottleneck on the P4's. Now they have Dual channel DDR boards which works sort of like rambus does. The board is using the ddr simulatneously and pretty much doubling the bandwidth So using 2 sticks of PC2100 is giving you close to PC4200 speeds thus feeding the chip and getting rid of the memory bottleneck.

[CaterpillarAssassin]

By dual and quad pumped what do u mean? Like the internal fsb is multiplied? I'm sorta confused I always knew it something to do with that but I never got a fully understanding of it.

[Jim Z]

"Double pumped" means DDR. Means that the data lines can transfer data synced to both the rising edge and falling edge of the clock signal. Normal SDR buses can only transfer data synced to the falling edge of the clock.

"Quad pumped" or QDR means that the data lines can transfer four times per clock signal. I'm not clear on how that's done, but there was an explanation posted elsewhere, if I find it I'll link it up.