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I read an article about Intel releasing ... a firmware update?? which allows you to throw a switch setting in CMOS causing NT/W2K etc to 'see' a second processor even tho only one is present. Or show 4 when only 2 are present. The article says they saw performance increases of perhaps 50% using this!
It allows the sysetm to use unused clock cycles effectively.
Has anybody seen it in the wild? Or read anything negative about it?

Ummm... I don't see how they can "recover" enough clock cycles to improve performance by 50%. I'd be sceptical but anything is possible.

You're thinking of Hyperthreading or Simultaneous Multi-Threading, which is available in the .13 micron Xeon (Prestonia.) It allows the processor to work on multiple threads at one time (similar to how two CPUs in an SMP box can work on different threads at the same time). Hyperthreading helps the CPU use it's resources more effectively, rather than having functional units sit there idle waiting for data. A Hyperthreading-enabled Xeon will appear as two "logical" CPUs in Windows Task manager.

Jim: That was it. and Bob, Intel claims only 30% but the magazine which tested it said they got as much as 50% on certain apps. They were surprised too, but everything I've seen these guys do has been true to date.

Well again I'd be doubtful, but it IS amazing what a skillful application of algorithms can accomplish so I won't totally dismiss it.

Well again I'd be doubtful, but it IS amazing what a skillful application of algorithms can accomplish so I won't totally dismiss it.

Jeeez. It's like a big part of you still lives in New York. :B

It is a really simple concept, really. Here is the skinny:

Stuff you probably know: A modern CPU is pipelined. The Intel P4 (which is a MHz whore, btw), sacrifices much of its possible performance for raw speed by having a monsterous 20 stage pipeline. The pipleline is where instructions are processed, but in distinct steps. 20 stages means it takes 20 steps to process an instruction. Well, there are latencies in certain instructions and wait periods when the processor has to let the memory get data for it. This time is basically wasted cycles that the CPU is doing nothing

Stuff you might not know: All mainstream processors use what is known as a PCB, or process control block. The PCB is where important info about a running process is located. Most importantly is the program counter. The program counter basically keeps track of where in memory the next instruction of a program is.

Ok, here is what SMT is: Simultaneous Multi Threading is when a single processor, with a single pipeline, keeps track of two program counters simultaneously. This means that the processor knows where the next instruction is for not one, but TWO threads. So if one thread needs to access memory or an I/O device and must waste time, the processor can load an instruction from the other program. It is relaly simple, and I cannot believe it is not already common. Ever since the pentium, processors have been wasting much of their time waiting on other stuff in your comptuer. By allowing the processor to keep itself busier, it is being used more fully.

I have actually heard of some processors (Alpha's I think) that had SMT long ago. I think the processors could pull instructions from any one of 4 threads.